The present invention relates to a method of producing a ferroelectric capacitor.
A ferroelectric memory (FeRAM; Ferroelectric Random Access Memory) is has a structure in which a selective transistor is connected to a ferroelectric capacitor having a ferroelectric layer in series. In general, the ferroelectric capacitor has an electrode formed of noble metal such as platinum and iridium and a dielectric layer formed of a ferroelectric such as lead zirconate titanate and strontium bismuth tantalate. The ferroelectric capacitor has been commercially available as a small capacity memory up to 64 kb. The ferroelectric capacitor has advantages of fast data writing and random access, and has been expected to replace a conventional non-volatile memory. Accordingly, it has been desired to develop the ferroelectric capacitor with a large capacity.
A method of producing the ferroelectric memory, in particular the ferroelectric capacitor, will be explained with reference to FIGS. 7(A) to 7(C) (refer to Patent References 1 and 2). FIGS. 7(A) to 7(C) are explanatory views showing a conventional method of producing the ferroelectric capacitor.
First, a capacitor forming laminated layer 530 is formed on a semiconductor substrate 510. The capacitor forming laminated layer 530 is formed of an interlayer insulating layer 320, a metal layer 531, a first conductive layer 533, a ferroelectric layer 535, and a second conductive layer 537, sequentially laminated, respectively. The semiconductor substrate 510 is provided with a silicon substrate 511 and an MOSFET 513 formed in an area defined by element separation insulating layers 512. The MOSFET 513 is formed of a drain area 514, a source area 515, a gate insulating layer 516, and a gate electrode 517. The interlayer insulating layer 520 is formed of an oxide layer, and is provided with a conductive plug 524.
In the next step, as shown in FIG. 7(B), a hard mask 552 is formed on the capacitor forming laminated layer 530 for covering an area for forming a ferroelectric capacitor with photo-lithography and dry etching. The hard mask 552 may be formed of SrRuO3 (SRO; refer to Patent Reference 1) or lead zirconate titanate (PZT; refer to Patent Reference 2).
In the next step, as shown in FIG. 7(C), the capacitor forming laminated layer 530 is shaped in a lamination 540 with a desired shape through dry etching using the hard mask 552. After the dry etching, a remaining portion of the metal layer 531 becomes a barrier metal 541; a remaining portion of the first conductive layer 533 becomes a lower electrode 543; a remaining portion of the ferroelectric layer 535 becomes a ferroelectric layer 545; and a remaining portion of the second conductive layer 537 becomes an upper electrode 547. The lamination 540 becomes the ferroelectric capacitor, and a memory cell of the ferroelectric memory is formed of the second conductive layer 537 and the lamination (the ferroelectric capacitor) 540.
Patent Reference 1; U.S. Pat. No. 6,495,413
Patent Reference 2; U.S. Pat. No. 6,423,592
In the conventional method of producing a ferroelectric capacitor, it is difficult to etch an electrode material of the lower electrode and the upper electrode, and the ferroelectric layer through the dry etching. Accordingly, in a case that the ferroelectric layer has a large thickness, or it is difficult to provide a large selectivity relative to a resist, a hard mask formed of silicon nitride or titanium nitride is used. Even when such a hard mask is used, it is still necessary to increase a thickness of the hard mask. When the hard mask has a large thickness, a dimension conversion difference increases. The dimension conversion difference has a larger influence as a size of a pattern decreases, thereby making it difficult to obtain a fine pattern necessary for producing a ferroelectric capacitor with high integration density.
Further, when a fine pattern is formed, since the size of a contact hole cannot be reduced under a design standard, an areal ratio of the contact hole relative to a capacitor area may become large. In this case, when the contact hole is opened through dry etching, there is a risk of damaging the ferroelectric capacitor. Such damage includes physical damage due to an electric stress such as charging and chemical damage due to a reducing gas passing through the upper electrode.
In view of the problems described above, an object of the present invention is to provide a method of producing a ferroelectric capacitor with a fine pattern and a small dimension conversion difference. Another object of the present invention is to provide a method of reducing damage generated at an opening of a contact hole formed on the ferroelectric capacitor.
Further objects and advantages of the invention will be apparent from the following description of the invention.